The present invention relates generally to the field of three-dimensional integrated circuits, and more particularly to soldering three-dimensional integrated circuits.
New integrated circuit technologies include three-dimensional integrated circuits (3D integrated circuits). In general, 3D integrated circuits include a plurality of vertically stacked dies, wherein the dies include processor dies, memory dies, or other types of logic dies. Through-silicon-vias (TSVs) and/or controlled collapse chip connections (C4s) connect the processor dies to a chip carrier. In a two-chip stack, for example, the bottom chip includes a plurality of TSVs that connect electronic elements of the top chip to the chip carrier. The connections are structurally strengthened by reflowing C4s (i.e., solder bumps) onto metallized contact pads on respective top surfaces of the bottom chip and the chip carrier. In some cases the C4s are a lead-free solder. Some 3D integrated circuits interface with an interposer that connects such integrated circuits to other computing devices.
3D integrated circuits provide numerous benefits. The benefits include increased areal transistor density, the ability to integrate heterogeneous dies (e.g., vertically stacking processor and memory dies), reduced power consumption, increased bandwidth (due to the ability to incorporate a large number of vias between layers), and shortened interconnections. Integrating memory dies into 3D integrated circuits takes advantage of reduced latencies provided by the relatively short lengths of TSV interconnects.